Interactive Engineering Simulators

Tactile Architecture & Systems Simulators

Eliminate rote memorization. Test memory addressing, instruction hazards, scheduling preemptions, and CIDR masks on live interactive silicon models.

1. Cache Splitter 2. 5-Stage Pipeline 3. CPU Scheduler 4. IPv4 Subnetting

Lab 01 • Computer Architecture

CPU Cache Address Splitter & Tag Directory Lab

GATE COA High-Yield (2-4 Marks every year)

Main Memory Size

Cache Capacity

Cache Block / Line Size

Associativity (\(k\)-Way)

Physical Address Bit Partition

Total: 32 Bits

TAG 18 Bits

SET INDEX 8 Bits

WORD OFFSET 6 Bits

Total Cache Lines 1024

Number of Sets 256

Lines Per Set 4

Tag Directory Overhead 2.5 KB

Live Address Decomposition Inspector

Binary: 0001 1010 0100 1111 0000 1000 1100 0100

Tag Value: 0x693C (18 bits) | Set Index: 35 (Set #35) | Word Offset: 4 (Byte 4)

Lab 02 • Microarchitecture

5-Stage Pipeline Hazard & CPI Visualizer

IF • ID • EX • MEM • WB Execution Timeline

Instruction Sequence

Operand Forwarding

Forwarding Enabled (EX-to-EX / MEM-to-EX)

Calculated CPI 1.25

Pipeline Speedup 3.20x

Instruction	C1	C2	C3	C4	C5	C6	C7	C8	C9	C10

Lab 03 • Operating Systems

Process Scheduling Gantt Generator

FCFS • Non-Preemptive SJF • SRTF • Round Robin

Scheduling Policy

Round Robin Time Quantum: 2 ms

Avg Waiting Time 3.00 ms

Avg Turnaround Time 7.50 ms

Live Timeline Gantt Chart

Process	Arrival Time (AT)	Burst Time (BT)	Completion Time (CT)	Turnaround Time (TAT)	Waiting Time (WT)

Lab 04 • Computer Networks

IPv4 CIDR & Subnet Breakdown Engine

Subnet Mask • Network ID • Directed Broadcast • Usable Range

IP Address

CIDR Prefix: /26 (26 Network Bits)

Subnet Mask 255.255.255.192

Network ID 192.168.10.0

Directed Broadcast 192.168.10.63

First Usable Host 192.168.10.1

Last Usable Host 192.168.10.62

Usable Hosts (\(2^H - 2\)) 62 Hosts

Binary Subnet Representation (32 Bits):

11111111.11111111.11111111.11000000

Green = Network & Subnet Bits (\(26\)) Orange = Host Bits (\(6\))